IC 74LS192

Counting Mode: Synchronous up/down BCD decade (0 to 9 counting sequence).

Dual Clocks: Separate inputs for Count-Up (CPU) and Count-Down (CPD).

Asynchronous Master Reset (MR): Clears all outputs to ⁠0⁠ (LOW) regardless of clock states.

Asynchronous Parallel Load (PL'): Allows pre-setting any desired 4-bit value (P_0 to P_3) onto the outputs using a LOW signal.

Terminal Count Outputs: Provides Carry (TCU') and Borrow (TCD') outputs for easy cascading without requiring external logic.

Package Type: Typically 16-pin Dual In-line Package (DIP).